New Zealand - Hamilton

New Language Evaluation

Project Aim

In common FPGA design flows circuits are designed using the VHDL language. This language is well-suited to the FPGA design task, but is low level. High level languages such as MyHDL and Chisel are becoming available for FPGAs and this project is to select one of these languages and evaluate how suitable it is for networking oriented FPGA designs by demonstrating design of a typical function, e.g. a packet protocol analyser.

Intern requirements

Degree in computer science or electrical engineering field with some experience in VHDL. An understanding of C++ and python and background in computer systems/embedded systems would be an advantage.


If you are interested in being considered for one of the above opportunities, please email with the reference Intern – Experience 2016. You will need to attach:
  • your CV showing details of projects you may have completed as part of your studies, and any work experience you have had
  • your academic transcript or equivalent
  • a covering letter outlining your key area of interest or specialization, and the project of most interest to you including a statement on what benefits your preferred project choice will have to your studies and future career path
Applications close 23 September 2016.

We offer

Competitive salaries and remuneration packages

A fun, vibrant and informal team environment

Flexible working conditions

Cutting edge technology and high-performance culture

A talented multinational workforce

Relocation packages for employees moving to NZ

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Working with a blue-chip client-base of global companies on mission-critical applications

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Winners of numerous awards including the Hi-tech Awards, NZ Engineering and Excellence and NZ Trade and Enterprise awards